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THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 1/26 thine electronics, inc. THC63LVD1023B 160mhz 67bits lvds transmitter general description the THC63LVD1023B transmitter is designed to suport single link transmission between host and flat panel display up to 1080p(60hz) resolutions and dual link transmission between host and flat panel display up to 1080p(120hz). the THC63LVD1023B converts 67bits of cmos/ttl data into lvds (low voltage differential signaling) data stream. the transmitter can be programmed for ris- ing edge or falling edge clocks through a dedicated pin, and support double edge inputs. in dual link, the transmit clock frequency of 160mhz, 67bits of rgb data are transmitted at an effective rate of 1.12gbps per lvds channel. in asynchronous mode, the THC63LVD1023B has 2 independent 35bits transmitter. features ? wide dot clock range suited for tv signal (480i- 1080p), pc signal (vga-qxga) ttl/cmos input: 10-160mhz lvds output: 20-160mhz ? pll requires no external components ? flexible input/output mode 1. single/dual ttl in , single/dual lvds out 2. double edge input for single ttl in/dual lvds out 3. input port sw for single ttl in/dual lvds out 4. asynchronous dual ttl in/dual lvds out ? clock edge selectable ? 3 lvds data mapping for simplifying pcb layout. ? pseudo random pattern generation circuit ? supports reduced swing lvds for low emi ? power down mode ? low power single 3.3v cmos design ? backward compatible with thc63lvd1023 ? 144pin lqfp block diagram parallel to serial pll ta1 +/- tb1 +/- tc1 +/- td1 +/- tclk1 +/- /pdwn (20 to 160mhz) transmitter clock in (10 to 160mhz) r1[9:0] lvds output te1 +/- 32 data port1 parallel to serial ta2 +/- tb2 +/- tc2 +/- td2 +/- te2 +/- tclk2 +/- port1 lvds output port2 g1[9:0] b1[9:0] cont1[2:1] hsync1 35 data formatter 35 r/f 1) demux 2) mux 3) distribution vsync1 de1 map r2[9:0] 32 data port2 g2[9:0] b2[9:0] cont2[2:1] 6 rs mode[3:0] prbs 4) ddr clkin1 clkin2 mux hsync2 vsync2 de2 5) input port sw 6) crosspoint async
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 2/26 thine electronics, inc. pin out (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 b27/td21 vcc b28/td22 b29/td23 hsync2/te20 vsync2/te21 de2/te22 vcc gnd clkin1 clkin2 cont11/te23 cont12/te24 cont21/te25 cont22/te26 r/f rs mode3 mode1 mode0 mode2 async /pdwn prbs reserved pgnd pvcc pgnd lgnd te2+ te2- td2+ td2- lgnd tclk2- tc2+ tc2- lgnd lvcc tb2+ tb2- ta2+ ta2- lgnd lgnd lgnd lgnd b16/td15 b15/td14 b14/td13 gnd vcc b13/td12 b12/td11 b11/td10 b10/tc16 g19/tc15 g18/tc14 g17/tc13 g16/tc12 g15/tc11 gnd vcc g14/tc10 g13/tb16 g12/tb15 g11/tb14 g10/tb13 r19/tb12 r18/tb11 r17/tb10 r16/ta16 gnd vcc r15/ta15 r14/ta14 r13/ta13 r12/ta12 r10/ta10 pgnd pvcc pgnd n/c b17/td16 b18/te10 b19/te11 vcc gnd r20/te12 r21/te13 r22/te14 r23/te15 r24/te16 r25/ta20 r26/ta21 r27/ta22 r28/ta23 r29/ta24 vcc gnd g20/ta25 g21/ta26 g22/tb20 g23/tb21 g24/tb22 g25/tb23 g26/tb24 g27/tb25 g28/tb26 g29/tc20 vcc gnd b20/tc21 b21/tc22 b22/tc23 b23/tc24 b24/tc25 b25/tc26 tclk2+ te1+ te1- td1+ td1- tc1+ tc1- tclk1+ tclk1- tb1+ tb1- ta1- ta1+ lvcc lvcc lvcc lvcc r11/ta11 b26/td20 gnd de1/td26 vsync1/td25 hsync1/td24 n/c map n/c
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 3/26 thine electronics, inc. pin description pin name pin # type description async=l async=h ta1+, ta1- 70, 71 lvds out the 1st link. the 1st pixel output data when dual-link. tb1+, tb1- 68, 69 tc1+, tc1- 64, 65 td1+, td1- 58, 59 te1+, te1- 56, 57 tclk1+, tclk1- 62, 63 lvds clock out for 1st and 2nd link. ta2+, ta2- 52, 53 the 2nd link. these pins are disabled when single link. tb2+, tb2- 50, 51 tc2+, tc2- 46, 47 td2+, td2- 40, 41 te2+, te2- 38, 39 tclk2+, tclk2- 44, 45 see following table. case1: lvds clock out for 2nd link. case2: lvds clock out for 1st link. case3: additional lvds clock out. identical to tclk1+/- case4: not available (high-impedance) r19 ~ r10 tb12~tb10, ta16~ta10 87 - 84, 81 - 76 in async=l the 1st pixel data inputs. async=h data inputs. g19 ~ g10 tc15~tc10, tb16~tb13 99 - 95, 92 - 88 b19 ~ b10 te11~te10, td16~td10, tc16 112 -110, 108 -106, 103 - 100 r29 ~ r20 ta24~ta20, te16~te12 124 - 115 in async=l the 2nd pixel data inputs. async=h data inputs. g29 ~ g20 tc20, tb26~tb20, ta26~ta25 136 - 127 b29 ~ b20 td23~td20, tc26~tc21 6, 5, 2, 1, 144 - 139 async mode0 mode1 mode2 description hx x lcase1 hx xhcase2 llxxcase3 lhl xcase4 lhhlcase4 lhhhcase3
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 4/26 thine electronics, inc. cont11 *1 , cont12 *1 te23,te24 17, 18 in async=l: control data inputs. async=h: data inputs. cont21 *1 , cont22 *1 te25,te26 19, 20 de1,de2 td26,te22 9,12 in async=l: data enable inputs. async=h: data inputs. vsync1, vsync2 td25,te21 8,11 in async=l: vsync inputs. async=h: data inputs hsync1, hsync2 td24,te20 7,10 in async=l: hsync inputs. async=h: data inputs clkin1 15 in clock input of following cases. clkin2 16 in clock input of following cases. r/f 21 in input clock triggering edge select. h: rising edge, l: falling edge rs 22 in lvds swing mode, v ref select. see fig4, 5. map (see fig7 to 9 and table4 to10) 24 in lvds mapping table select. mode1, mode0 25, 26 in pin name pin # type description async=l async=h async mode1 mode0 mode3 hx x x ll x x lhlh lhh x async mode1 mode0 mode3 hx x x lh l l rs lvds swing small swing input support v ihm 350mv n/a v imm 350mv rs=v ref a v ilm 200mv n/a a. v ref is input reference voltage. map mapping mode v ihm mapping mode1 v ilm mapping mode2 v imm mapping mode3 pixel data mode. mode1 mode0 mode l l dual link (dual-in/dual-out) h l dual link (single-in/dual-out) l h single link (dual-in/single-out) h h single link (single-in/single-out) pin description (continued) *1: cont## are data pins that us er can use as data like rgb data.
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 5/26 thine electronics, inc. * 2: setting the prbs pin high enables th e internal test pattern generator. it generates pseudo-random bit sequence of 2 23 -1. the generated prbs is fed into input data latches, form atted as vga video like data , encoded and serialized into txout output. this func tion is normally to be used for analyzi ng the signal integrity of the transmission channel including pcb traces, connectors, and cables. mode2 (see fig.5) 27 in the use of these multi-functi on depends on the setting of mode<1:0> or async. async=h(mode<1:0>=don?t care.) h: cross point switching enable. l: cross point switching disable. async=l mode<1:0>=hh(single-in/single-out mode) h: distribution function enable. l: distribution function disable. mode<1:0>=hl(single-in/dual-out mode) h: ddr (double edge input) function enable. l: ddr (double edge input) function disable. mode3 23 in input port switching function enable when mode<1:0>=hl(single-in/dual-out mode). h or open: port switch disable. l: port switch enable. async 28 in asynchronous function enable. h: asynchronous mode enable.(mode<1 :0>=disable) l: asynchronous mode disable.(mode<1:0>=enable) /pdwn 30 in h: normal operation, l: power down (all outputs are hi-z) prbs *2 31 in prbs (pseudo-random binary sequence) generator is active in order to evaluate eye patterns when mode<1:0> = ll (dual-in /dual-out mode) or async=h h: prbs generator is enable. l: normal operation reserved 32 in must be tied to gnd. n/c 29, 33, 109 must be open. vcc 3, 13, 82, 93, 104, 113, 125, 137 power power supply pins for ttl inputs and digital circuitry. gnd 4, 14, 83, 94, 105, 114, 126, 138 ground ground pins for ttl inputs and digital circuitry. lvcc 43, 49, 55, 61, 67 power power supply pins for lvds outputs. lgnd 37, 42, 48, 54, 60, 66, 72 ground ground pins for lvds outputs. pvcc 35, 74 power power supply pins for pll circuitry. pgnd 34, 36, 73, 75 ground ground pins for pll circuitry. pin name pin # type description async=l async=h
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 6/26 thine electronics, inc. absolute maximum ratings recommended operating conditions supply voltage (v cc ) -0.3v ~ +4.0v cmos/ttl input voltage -0.3v ~ (v cc + 0.3v) lvds driver output voltage -0.3v ~ (v cc + 0.3v) output current -30ma ~ 30ma junction temperature +125 storage temperature range -55 ~ +125 reflow peak temperature / time +260 / 10sec. maximum power dissipation @+25 2.4w parameter min. typ max units all supply voltage 3.0 3.3 3.6 v operating ambient temperature -20 70 clock frequency mode<1:0>=ll dual-in/dual-out input 20 160 mhz lvds output 20 160 mhz mode<1:0>=lh dual-in/single-out input 10 80 mhz lvds output 20 160 mhz mode<1:0>=hl single-in/dual-out single edge input (mode2=l) input 40 160 mhz lvds output 20 80 mhz double edge input (mode2=h) input 20 80 mhz lvds output 20 80 mhz mode<1:0>=hh single-in/single-out input 20 160 mhz lvds output 20 160 mhz async=h asynchronous mode input 20 160 mhz lvds output 20 160 mhz c c c c c c
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 7/26 thine electronics, inc. electrical characteristics cmos/ttl dc specifications v cc = vcc=pvcc=lvcc lvds transmitter dc specifications v cc = vcc=pvcc=lvcc symbol parameter conditions min. typ. max. units v ih a a. clkin1,r10~r19,g10~g19,b10~b 19,de1,hsync1,vsync1,cont11,cont12 clkin2,r20~r29,g20~g29,b20~ b29,de2,hsync2,vsy nc2,cont21,cont22 high level data input voltage rs=v cc or gnd 2.0 v cc v rs=0.6~1.4v v ref b +0.1 b. v ref is input voltage of rs pin. v v il a low level data input voltage rs=v cc or gnd gnd 0.8 v rs=0.6~1.4v v ref -0.1 v v ihc c c. r/f,mode0,mode1,mode2,mode3,pdwn,prbs,async high level control input voltage 2.0 v cc v v ilc c low level control input voltage gnd 0.8 v v ihm d high level control input voltage 0.8v cc v cc v v imm d d. rs,map middle level control input voltage 0.6 1.4 v v ilm d low level control input voltage gnd 0.08v cc v i inc input current (except mode3) a i incm3 input current (only mode3) a symbol parameter conditions min. typ. max. units vod differential ou tput voltage rl=100 normal swing rs= v cc 250 350 450 mv reduced swing rs= gnd 100 200 300 mv vod change in vod between complementary output states rl=100 35 mv voc common mode voltage 1.125 1.25 1.375 v voc change in voc between complementary output states 35 mv i os output short circuit cu rrent vout=gnd, rl=100 -24 ma i oz output tri-state current /pdwn=gnd, vout=gnd to v cc a gnd v in v cc ? 10 gnd v in v c c ? 20 10
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 8/26 thine electronics, inc. electrical characte ristics (continued) supply current v cc = vcc=pvcc=lvcc symbol parameter condition typ. max. units i tccw transmitter supply current (worst case pattern) fig1. rl=100 cl=5pf rs=v cc mode<1:0>=hh single-in/single-out mode2=l distribution off clkin1=65mhz 105 ma clkin1=85mhz 121 ma clkin1=135mhz 157 ma clkin1=160mhz 179 ma mode<1:0>=hh single-in/single-out mode2=h distribution on clkin1=65mhz 146 ma clkin1=85mhz 172 ma clkin1=135mhz 217 ma clkin1=160mhz 250 ma mode<1:0>=hl single-in/dual-out mode2=l mode3=h or l ddr input off clkin1/2=65mhz 108 ma clkin1/2=85mhz 136 ma clkin1/2=135mhz 169 ma clkin1/2=160mhz 194 ma mode<1:0>=hl single-in/dual-out mode2=h mode3=h or l ddr input on clkin1/2=32.5mhz 120 ma clkin1/2=42.5mhz 140 ma clkin1/2=67.5mhz 183 ma clkin1/2=80mhz 199 ma mode<1:0>=lh dual-in/single-out clkin1=32.5mhz 95 ma clkin1=42.5mhz 110 ma clkin1=67.5mhz 143 ma clkin1=80mhz 166 ma mode<1:0>=ll dual-in/dual-out clkin1=65mhz 167 ma clkin1=85mhz 197 ma clkin1=135mhz 261 ma clkin1=160mhz 301 ma async=h asynchronous clkin1/2=65mhz 183 ma clkin1/2=85mhz 214 ma clkin1/2=135mhz 286 ma clkin1=160mhz 329 ma i tccs transmitter power down supply current /pdwn = l, all inputs = fixed l or h 50 a fig1. test pattern (lvds output full toggle pattern) txy+ x= a, b, c, d, e y=1,2 tclk1+
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 9/26 thine electronics, inc. switching characteristics v cc = vcc=pvcc=lvcc symbol parameter min. typ. max. units t tcip clk in period(fig4,5) 6.25 100 ns t tch clk in high time(fig4,5) 0.35t tcip 0.5t tcip 0.65t tcip ns t tcl clk in low time(fig4,5) 0.35t tcip 0.5t tcip 0.65t tcip ns t ts ttl data setup to clk in(fig4,5) 2.5 ns t th ttl data hold from ckl in(fig4,5) 0.0 ns t tcd clk in to tclk+/- delay(fig4,5) mode<1:0>=ll dual-in/dual-out (4+3/7)t tcip +2.6 (4+3/7)t tcip +7.5 ns t tcop clk out period(fig6) 6.25 50 ns t lvt lvds transition time(fig2) 0.6 1.5 ns t top1 output data position0 (fig6) t tcop = 6.25ns~20ns -0.15 0.0 +0.15 ns t top0 output data position1 (fig6) ns t top6 output data position2 (fig6) ns t top5 output data position3 (fig6) ns t top4 output data position4 (fig6) ns t top3 output data position5 (fig6) ns t top2 output data position6 (fig6) ns t tpll pll lock time(fig3) 10.0 ms t deint de input period (fig3-1) single-in / dual-out, ddr off mode only(mode<2:0>=lhl) 4t tcip ttcip*(2n) a a. refer to fig3-1 for details. ns t deh de high time (fig3-1) single-in / dual-out, ddr off mode only(mode<2:0>=lhl) 2t tcip ttcip*(2m) a ns t del de low time(fig3-1) single-in / dual-out, ddr off mode only(mode<2:0>=lhl) 2t tcip ns t tcop 7 --------------- 0 . 1 5 ? t tcop 7 --------------- t tcop 7 --------------- 0 . 1 5 + 2 t tcop 7 --------------- 0 . 1 5 ? 2 t tcop 7 --------------- 2 t tcop 7 --------------- 0 . 1 5 + 3 t tcop 7 --------------- 0 . 1 5 ? 3 t tcop 7 --------------- 3 t tcop 7 --------------- 0 . 1 5 + 4 t tcop 7 --------------- 0 . 1 5 ? 4 t tcop 7 --------------- 4 t tcop 7 --------------- 0 . 1 5 + 5 t tcop 7 --------------- 0 . 1 5 ? 5 t tcop 7 --------------- 5 t tcop 7 --------------- 0 . 1 5 + 6 t tcop 7 --------------- 0 . 1 5 ? 6 t tcop 7 --------------- 6 t tcop 7 --------------- 0 . 1 5 +
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 10/26 thine electronics, inc. ac timing diagrams 2.0v t tpll clkinx /pdwn tclkx+/- v diff =0v fig3. pll lock time x=1,2 x=1,2 5pf 20% 80% 20% 80% t lvt t lvt v diff 100 v diff =(ta+)-(ta-) ta+ ta- lvds output load fig2. lvds output load and transition time clkin de t deint t deh t del note: in single-in/dual-out, ddr off mode (mode<2:0>=lhl), the period between rising edges of de (t deint ), high time of de (t deh ) t deint = ttcip * (2n) m, n =integer t tcip fig3-1. single in / dual out, ddr off mode de input timing should always satisf y following equations. t deh = ttcip * (2m)
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 11/26 thine electronics, inc. fig4. clkin period, high/low time, setup/hold timing t tcip t ts t th t tch t tcl clkinx t tcd voc v ref v ref v ref v ref v ref note: clkinx: for r/f=gnd, denote as solid line, for r/f=vcc, denote as dashed line. rs pin vod vref v ihm 350mv vcc/2 v imm input voltage of rs pin v ilm 200mv vcc/2 gnd gnd x=1,2 rxn, gxn, bxn hsyncx vsyncx dex contx1 contx2 x=1,2 n=0-9 current data tclkx+/- x=1,2 current data txy+/- x=1,2 y= a, b, c, d, e x=1,2 vod vcc vcc fig5. clkin period, high/low time , setup/hold timing for double edge input mode (ddr) note: clkinx: for r/f=gnd, denote as solid line, for r/f=vcc, denote as dashed line. mode<1:0>=hl, mode2=h x=1,2 current data txy+/- x=1,2 y= a, b, c, d, e v ref v ref 1st pixel data 2nd pixel data gnd vod vcc vcc rs pin vod vref v ihm 350mv vcc/2 v imm input voltage of rs pin v ilm 200mv vcc/2 gnd ac timing diagrams (continued) t ts t th t ts t th t tcip t tch t tcl clkinx t tcd voc v ref v ref v ref x=1,2 rxn, gxn, bxn hsyncx vsyncx dex contx1 contx2 x=1,2 n=0-9 tclkx+/- x=1,2
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 12/26 thine electronics, inc. ac timing diagrams (continued) v diff = 0v tyx+/- tyx6 tyx5 tyx4 tyx3 tyx2 tyx1 tyx0 tyx6 tyx5 tyx4 tyx3 tyx2 tyx1 v diff = 0v t top2 t top3 t top4 t top5 t top6 t top0 t top1 t tcop tclkx+ x = 1,2 y = a,b,c,d,e note: v diff = (tyx+) - (tyx-), (tclkx+) - (tclkx-) fig6. lvds output data position
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 13/26 thine electronics, inc. input data mapping ? table1. input color data naming rule ? table2. ttl/cmos input data mapping (single-in mode, mode1=h) x y z description x=r red color data x=g green color data x=b blue color data y= none single pixel y=e dual pixel 1st pixel data y=o 2nd pixel data z=0-9 bit number 0: lsb (least significant bit) 9: msb (most significant bit) data signals transmitter input pin names 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit r0 r10 r1 r11 r2 r0 r12 r12 r3 r1 r13 r13 r4 r2 r0 r14 r14 r14 r5 r3 r1 r15 r15 r15 r6 r4 r2 r16 r16 r16 r7 r5 r3 r17 r17 r17 r8 r6 r4 r18 r18 r18 r9 r7 r5 r19 r19 r19 g0 g10 g1 g11 g2 g0 g12 g12 g3 g1 g13 g13 g4 g2 g0 g14 g14 g14 g5 g3 g1 g15 g15 g15 g6 g4 g2 g16 g16 g16 g7 g5 g3 g17 g17 g17 g8 g6 g4 g18 g18 g18 g9 g7 g5 g19 g19 g19 b0 b10 b1 b11 b2 b0 b12 b12 b3 b1 b13 b13 b4 b2 b0 b14 b14 b12 b5 b3 b1 b15 b15 b13 b6 b4 b2 b16 b16 b14 b7 b5 b3 b17 b17 b15 b8 b6 b4 b18 b18 b16 b9 b7 b5 b19 b19 b17
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 14/26 thine electronics, inc. input data mapping (continued) ? table3. ttl/cmos input data mapping (dual-in mode, mode1=l) data signals transmitter input pin names data signals transmitter input pin names 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit re0 r10 ro0 r20 re1 r11 ro1 r22 re2 re0 r12 r12 ro2 ro0 r22 r22 re3 re1 r13 r13 ro3 ro1 r23 r23 re4 re2 re0 r14 r14 r14 ro4 ro2 ro0 r24 r24 r24 re5 re3 re1 r15 r15 r15 ro5 ro3 ro1 r25 r25 r25 re6 re4 re2 r16 r16 r16 ro6 ro4 ro2 r26 r26 r26 re7 re5 re3 r17 r17 r17 ro7 ro5 ro3 r27 r27 r27 re8 re6 re4 r18 r18 r18 ro8 ro6 ro4 r28 r28 r28 re9 re7 re5 r19 r19 r19 ro9 ro7 ro5 r29 r29 r29 ge0 g10 go0 g20 ge1 g11 go1 g22 ge2 ge0 g12 g12 go2 go0 g22 g22 ge3 ge1 g13 g13 go3 go1 g23 g23 ge4 ge2 ge0 g14 g14 g14 go4 go2 go0 g24 g24 g24 ge5 ge3 ge1 g15 g15 g15 go5 go3 go1 g25 g25 g25 ge6 ge4 ge2 g16 g16 g16 go6 go4 go2 g26 g26 g26 ge7 ge5 ge3 g17 g17 g17 go7 go5 go3 g27 g27 g27 ge8 ge6 ge4 g18 g18 g18 go8 go6 go4 g28 g28 g28 ge9 ge7 ge5 g19 g19 g19 go9 go7 go5 g29 g29 g29 be0 b10 bo0 b20 be1 b11 bo1 b22 be2 be0 b12 b12 bo2 bo0 b22 b22 be3 be1 b13 b13 bo3 bo1 b23 b23 be4 be2 be0 b14 b14 b14 bo4 bo2 bo0 b24 b24 b24 be5 be3 be1 b15 b15 b15 bo5 bo3 bo1 b25 b25 b25 be6 be4 be2 b16 b16 b16 bo6 bo4 bo2 b26 b26 b26 be7 be5 be3 b17 b17 b17 bo7 bo5 bo3 b27 b27 b27 be8 be6 be4 b18 b18 b18 bo8 bo6 bo4 b28 b28 b28 be9 be7 be5 b19 b19 b19 bo9 bo7 bo5 b29 b29 b29
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 15/26 thine electronics, inc. lvds output data mapping tx1+/- tclk1+ previous cycle current cycle fig7. ttl data inputs mapped to lvds outputs mode0= h (single-out mode) x= a, b, c, d, e tx11(n-1) tx10(n-1) tx16(n) tx15(n) tx14(n) tx13(n) tx12(n) tx11(n) tx10(n) tx16(n+1) (2nd pixel data) (1st pixel data) next cycle (2nd pixel data) tx1+/- tclk1+ previous cycle current cycle fig8. ttl data inputs mapped to lvds outputs mode0= l (dual-out mode) x= a, b, c, d, e tx11(n-1) tx10(n-1) tx16(n) tx15(n) tx14(n) tx13(n) tx12(n) tx11(n) tx10(n) tx16(n+1) tx21(n-1) tx20(n-1) tx26(n) tx25(n) tx24(n) tx23(n) tx22(n) tx21(n) tx20(n) tx26(n+1) tx2+/- x= a, b, c, d, e next cycle
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 16/26 thine electronics, inc. lvds output data mapping (continued) ? table4. lvds output data mapping (single-in/sin gle-out distribution off, mode<1:0>=hh, mode2=l) lvds output data mapping mode (input pin name) mode1 map=v ihm mode2 map=v ilm mode3 map=v imm ta10 r14 r12 r10 ta11 r15 r13 r11 ta12 r16 r14 r12 ta13 r17 r15 r13 ta14 r18 r16 r14 ta15 r19 r17 r15 ta16 g14 g12 g10 tb10 g15 g13 g11 tb11 g16 g14 g12 tb12 g17 g15 g13 tb13 g18 g16 g14 tb14 g19 g17 g15 tb15 b14 b12 b10 tb16 b15 b13 b11 tc10 b16 b14 b12 tc11 b17 b15 b13 tc12 b18 b16 b14 tc13 b19 b17 b15 tc14 hsync1 hsync1 hsync1 tc15 vsync1 vsync1 vsync1 tc16 de1 de1 de1 td10 r12 r18 r16 td11 r13 r19 r17 td12 g12 g18 g16 td13 g13 g19 g17 td14 b12 b18 b16 td15 b13 b19 b17 td16 cont11 cont11 cont11 te10 r10 r10 r18 te11 r11 r11 r19 te12 g10 g10 g18 te13 g11 g11 g19 te14 b10 b10 b18 te15 b11 b11 b19 te16 cont12 cont12 cont12
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 17/26 thine electronics, inc. lvds output data mapping (continued) ? table5. lvds output data mapping (single-in/s ingle-out distribution on, mode<1:0>=hh, mode2=h) lvds output data (1st link) mapping mode (input pin name) lvds output data (2nd link) mapping mode (input pin name) mode1 map=v ihm mode2 map=v ilm mode3 map=v imm mode1 map=v ihm mode2 map=v ilm mode3 map=v imm ta10 r14 r12 r10 ta20 r14 r12 r10 ta11 r15 r13 r11 ta21 r15 r13 r11 ta12 r16 r14 r12 ta22 r16 r14 r12 ta13 r17 r15 r13 ta23 r17 r15 r13 ta14 r18 r16 r14 ta24 r18 r16 r14 ta15 r19 r17 r15 ta25 r19 r17 r15 ta16 g14 g12 g10 ta26 g14 g12 g10 tb10 g15 g13 g11 tb20 g15 g13 g11 tb11 g16 g14 g12 tb21 g16 g14 g12 tb12 g17 g15 g13 tb22 g17 g15 g13 tb13 g18 g16 g14 tb23 g18 g16 g14 tb14 g19 g17 g15 tb24 g19 g17 g15 tb15 b14 b12 b10 tb25 b14 b12 b10 tb16 b15 b13 b11 tb26 b15 b13 b11 tc10 b16 b14 b12 tc20 b16 b14 b12 tc11 b17 b15 b13 tc21 b17 b15 b13 tc12 b18 b16 b14 tc22 b18 b16 b14 tc13 b19 b17 b15 tc23 b19 b17 b15 tc14 hsync1 hsync1 hsync1 tc24 hsync1 hsync1 hsync1 tc15 vsync1 vsync1 vsync1 tc25 vsync1 vsync1 vsync1 tc16 de de de1 tc26 de de de1 td10 r12 r18 r16 td20 r12 r18 r16 td11 r13 r19 r17 td21 r13 r19 r17 td12 g12 g18 g16 td22 g12 g18 g16 td13 g13 g19 g17 td23 g13 g19 g17 td14 b12 b18 b16 td24 b12 b18 b16 td15 b13 b19 b17 td25 b13 b19 b17 td16 cont11 cont11 cont11 td26 cont11 cont11 cont11 te10 r10 r10 r18 te20 r10 r10 r18 te11 r11 r11 r19 te21 r11 r11 r19 te12 g10 g10 g18 te22 g10 g10 g18 te13 g11 g11 g19 te23 g11 g11 g19 te14 b10 b10 b18 te24 b10 b10 b18 te15 b11 b11 b19 te25 b11 b11 b19 te16 cont12 cont12 cont12 te26 cont12 cont12 cont12
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 18/26 thine electronics, inc. lvds output data mapping (continued) ? ta b l e 6 . lv d s o u t p u t d a t a m a p p i n g (single-in/dual-out, ddr on or off, port switch of f, mode<1:0>=hl, mode2=h or l, mode3=h or open) lvds output data (1st link) mapping mode (input pin name) lvds output data (2nd link) mapping mode (input pin name) mode1 map=v ihm mode2 map=v ilm mode3 map=v imm mode1 map=v ihm mode2 map=v ilm mode3 map=v imm ta10 r14 r12 r10 ta20 r14 r12 r10 ta11 r15 r13 r11 ta21 r15 r13 r11 ta12 r16 r14 r12 ta22 r16 r14 r12 ta13 r17 r15 r13 ta23 r17 r15 r13 ta14 r18 r16 r14 ta24 r18 r16 r14 ta15 r19 r17 r15 ta25 r19 r17 r15 ta16 g14 g12 g10 ta26 g14 g12 g10 tb10 g15 g13 g11 tb20 g15 g13 g11 tb11 g16 g14 g12 tb21 g16 g14 g12 tb12 g17 g15 g13 tb22 g17 g15 g13 tb13 g18 g16 g14 tb23 g18 g16 g14 tb14 g19 g17 g15 tb24 g19 g17 g15 tb15 b14 b12 b10 tb25 b14 b12 b10 tb16 b15 b13 b11 tb26 b15 b13 b11 tc10 b16 b14 b12 tc20 b16 b14 b12 tc11 b17 b15 b13 tc21 b17 b15 b13 tc12 b18 b16 b14 tc22 b18 b16 b14 tc13 b19 b17 b15 tc23 b19 b17 b15 tc14 hsync1 hsync1 hsync1 tc24 hsync1 hsync1 hsync1 tc15 vsync1 vsync1 vsync1 tc25 vsync1 vsync1 vsync1 tc16 de1 de1 de1 tc26 de1 de1 de1 td10 r12 r18 r16 td20 r12 r18 r16 td11 r13 r19 r17 td21 r13 r19 r17 td12 g12 g18 g16 td22 g12 g18 g16 td13 g13 g19 g17 td23 g13 g19 g17 td14 b12 b18 b16 td24 b12 b18 b16 td15 b13 b19 b17 td25 b13 b19 b17 td16 cont11 cont11 cont11 td26 cont11 cont11 cont11 te10 r10 r10 r18 te20 r10 r10 r18 te11 r11 r11 r19 te21 r11 r11 r19 te12 g10 g10 g18 te22 g10 g10 g18 te13 g11 g11 g19 te23 g11 g11 g19 te14 b10 b10 b18 te24 b10 b10 b18 te15 b11 b11 b19 te25 b11 b11 b19 te16 cont12 cont12 cont12 te26 cont12 cont12 cont12
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 19/26 thine electronics, inc. lvds output data mapping (continued) ? ta b l e 7 . lv d s o u t p u t d a t a m a p p i n g (single-in/dual-out, ddr on or off, port swit ch on, mode<1:0>=hl, mode2=h or l, mode3=l) lvds output data (1st link) mapping mode (input pin name) lvds output data (2nd link) mapping mode (input pin name) mode1 map=v ihm mode2 map=v ilm mode3 map=v imm mode1 map=v ihm mode2 map=v ilm mode3 map=v imm ta10 r24 r22 r20 ta20 r24 r22 r20 ta11 r25 r23 r21 ta21 r25 r23 r21 ta12 r26 r24 r22 ta22 r26 r24 r22 ta13 r27 r25 r23 ta23 r27 r25 r23 ta14 r28 r26 r24 ta24 r28 r26 r24 ta15 r29 r27 r25 ta25 r29 r27 r25 ta16 g24 g22 g20 ta26 g24 g22 g20 tb10 g25 g23 g21 tb20 g25 g23 g21 tb11 g26 g24 g22 tb21 g26 g24 g22 tb12 g27 g25 g23 tb22 g27 g25 g23 tb13 g28 g26 g24 tb23 g28 g26 g24 tb14 g29 g27 g25 tb24 g29 g27 g25 tb15 b24 b22 b20 tb25 b24 b22 b20 tb16 b25 b23 b21 tb26 b25 b23 b21 tc10 b26 b24 b22 tc20 b26 b24 b22 tc11 b27 b25 b23 tc21 b27 b25 b23 tc12 b28 b26 b24 tc22 b28 b26 b24 tc13 b29 b27 b25 tc23 b29 b27 b25 tc14 hsync2 hsync2 hsync2 tc24 hsync2 hsync2 hsync2 tc15 vsync2 vsync2 vsync2 tc25 vsync2 vsync2 vsync2 tc16 de2 de2 de2 tc26 de2 de2 de2 td10 r22 r28 r26 td20 r22 r28 r26 td11 r23 r29 r27 td21 r23 r29 r27 td12 g22 g28 g26 td22 g22 g28 g26 td13 g23 g29 g27 td23 g23 g29 g27 td14 b22 b28 b26 td24 b22 b28 b26 td15 b23 b29 b27 td25 b23 b29 b27 td16 cont21 cont21 cont21 td26 cont21 cont21 cont21 te10 r20 r20 r28 te20 r20 r20 r28 te11 r21 r21 r29 te21 r21 r21 r29 te12 g20 g20 g28 te22 g20 g20 g28 te13 g21 g21 g29 te23 g21 g21 g29 te14 b20 b20 b28 te24 b20 b20 b28 te15 b21 b21 b29 te25 b21 b21 b29 te16 cont22 cont22 cont22 te26 cont22 cont22 cont22
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 20/26 thine electronics, inc. lvds output data mapping (continued) ? table8. lvds output data mapping (dual-in/single-out, mode<1:0>=lh) lvds output data (1st pixel) mapping mode (input pin name) lvds output data (2nd pixel) mapping mode (input pin name) mode1 map=v ihm mode2 map=v ilm mode3 map=v imm mode1 map=v ihm mode2 map=v ilm mode3 map=v imm ta10(n) r14 r12 r10 ta10(n+1) r24 r22 r20 ta11(n) r15 r13 r11 ta11(n+1) r25 r23 r21 ta12(n) r16 r14 r12 ta12(n+1) r26 r24 r22 ta13(n) r17 r15 r13 ta13(n+1) r27 r25 r23 ta14(n) r18 r16 r14 ta14(n+1) r28 r26 r24 ta15(n) r19 r17 r15 ta15(n+1) r29 r27 r25 ta16(n) g14 g12 g10 ta16(n+1) g24 g22 g20 tb10(n) g15 g13 g11 tb10(n+1) g25 g23 g21 tb11(n) g16 g14 g12 tb11(n+1) g26 g24 g22 tb12(n) g17 g15 g13 tb12(n+1) g27 g25 g23 tb13(n) g18 g16 g14 tb13(n+1) g28 g26 g24 tb14(n) g19 g17 g15 tb14(n+1) g29 g27 g25 tb15(n) b14 b12 b10 tb15(n+1) b24 b22 b20 tb16(n) b15 b13 b11 tb16(n+1) b25 b23 b21 tc10(n) b16 b14 b12 tc10(n+1) b26 b24 b22 tc11(n) b17 b15 b13 tc11(n+1) b27 b25 b23 tc12(n) b18 b16 b14 tc12(n+1) b28 b26 b24 tc13(n) b19 b17 b15 tc13(n+1) b29 b27 b25 tc14(n) hsync1 hsync1 hsync1 tc14(n+1) hsync1 hsync1 hsync1 tc15(n) vsync1 vsync1 vsync1 tc15(n+1) vsync1 vsync1 vsync1 tc16(n) de1 de1 de1 tc16(n+1) de1 de1 de1 td10(n) r12 r18 r16 td10(n+1) r22 r28 r26 td11(n) r13 r19 r17 td11(n+1) r23 r29 r27 td12(n) g12 g18 g16 td12(n+1) g22 g28 g26 td13(n) g13 g19 g17 td13(n+1) g23 g29 g27 td14(n) b12 b18 b16 td14(n+1) b22 b28 b26 td15(n) b13 b19 b17 td15(n+1) b23 b29 b27 td16(n) cont11 cont11 cont11 td 16(n+1) cont21 cont21 cont21 te10(n) r10 r10 r18 te10(n+1) r20 r20 r28 te11(n) r11 r11 r19 te11(n+1) r21 r21 r29 te12(n) g10 g10 g18 te12(n+1) g20 g20 g28 te13(n) g11 g11 g19 te13(n+1) g21 g21 g29 te14(n) b10 b10 b18 te14(n+1) b20 b20 b28 te15(n) b11 b11 b19 te15(n+1) b21 b21 b29 te16(n) cont12 cont12 cont12 te16(n+1) cont22 cont22 cont22
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 21/26 thine electronics, inc. lvds output data mapping (continued) ? table9. lvds output data mapping (dual-in/dual-out, mode<1:0>=ll) lvds output data (1st link) mapping mode (input pin name) lvds output data (2nd link) mapping mode (input pin name) mode1 map=v ihm mode2 map=v ilm mode3 map=v imm mode1 map=v ihm mode2 map=v ilm mode3 map=v imm ta10 r14 r12 r10 ta20 r24 r22 r20 ta11r15r13r11ta21r25r23r21 ta12 r16 r14 r12 ta22 r26 r24 r22 ta13 r17 r15 r13 ta23 r27 r25 r23 ta14 r18 r16 r14 ta24 r28 r26 r24 ta15 r19 r17 r15 ta25 r29 r27 r25 ta16 g14 g12 g10 ta26 g24 g22 g20 tb10 g15 g13 g11 tb20 g25 g23 g21 tb11 g16 g14 g12 tb21 g26 g24 g22 tb12 g17 g15 g13 tb22 g27 g25 g23 tb13 g18 g16 g14 tb23 g28 g26 g24 tb14 g19 g17 g15 tb24 g29 g27 g25 tb15 b14 b12 b10 tb25 b24 b22 b20 tb16 b15 b13 b11 tb26 b25 b23 b21 tc10 b16 b14 b12 tc20 b26 b24 b22 tc11 b17 b15 b13 tc21 b27 b25 b23 tc12 b18 b16 b14 tc22 b28 b26 b24 tc13 b19 b17 b15 tc23 b29 b27 b25 tc14 hsync1 hsync1 hsync1 tc24 hsync1 hsync1 hsync1 tc15 vsync1 vsync1 vsync1 tc25 vsync1 vsync1 vsync1 tc16 de1 de1 de1 tc26 de1 de1 de1 td10 r12 r18 r16 td20 r22 r28 r26 td11 r13 r19 r17 td21 r23 r29 r27 td12 g12 g18 g16 td22 g22 g28 g26 td13 g13 g19 g17 td23 g23 g29 g27 td14 b12 b18 b16 td24 b22 b28 b26 td15 b13 b19 b17 td25 b23 b29 b27 td16 cont11 cont11 cont11 td26 cont21 cont21 cont21 te10 r10 r10 r18 te20 r20 r20 r28 te11 r11 r11 r19 te21 r21 r21 r29 te12 g10 g10 g18 te22 g20 g20 g28 te13 g11 g11 g19 te23 g21 g21 g29 te14 b10 b10 b18 te24 b20 b20 b28 te15 b11 b11 b19 te25 b21 b21 b29 te16 cont12 cont12 cont12 te26 cont22 cont22 cont22
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 22/26 thine electronics, inc. lvds output data mapping (continued) ? table10. lvds output data mapping (asynchro nous cross point switching off, async=h mode2=l) lvds output data (1st link) mapping (map= don?t care) (input pin name) lvds output data (2nd link) mapping (map= don?t care) (input pin name) ta10 ta10 ta20 ta20 ta11 ta11 ta21 ta21 ta12 ta12 ta22 ta22 ta13 ta13 ta23 ta23 ta14 ta14 ta24 ta24 ta15 ta15 ta25 ta25 ta16 ta16 ta26 ta26 tb10 tb10 tb20 tb20 tb11 tb11 tb21 tb21 tb12 tb12 tb22 tb22 tb13 tb13 tb23 tb23 tb14 tb14 tb24 tb24 tb15 tb15 tb25 tb25 tb16 tb16 tb26 tb26 tc10 tc10 tc20 tc20 tc11 tc11 tc21 tc21 tc12 tc12 tc22 tc22 tc13 tc13 tc23 tc23 tc14 tc14 tc24 tc24 tc15 tc15 tc25 tc25 tc16 tc16 tc26 tc26 td10 td10 td20 td20 td11 td11 td21 td21 td12 td12 td22 td22 td13 td13 td23 td23 td14 td14 td24 td24 td15 td15 td25 td25 td16 td16 td26 td26 te10 te10 te20 te20 te11 te11 te21 te21 te12 te12 te22 te22 te13 te13 te23 te23 te14 te14 te24 te24 te15 te15 te25 te25 te16 te16 te26 te26
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 23/26 thine electronics, inc. lvds output data mapping (continued) ? table11. lvds output data mapping (asynchron ous cross point switching on, async=h mode2=h) lvds output data (1st link) mapping (map= don?t care) (input pin name) lvds output data (2nd link) mapping (map= don?t care) (input pin name) ta10 ta20 ta20 ta10 ta11 ta21 ta21 ta11 ta12 ta22 ta22 ta12 ta13 ta23 ta23 ta13 ta14 ta24 ta24 ta14 ta15 ta25 ta25 ta15 ta16 ta26 ta26 ta16 tb10 tb20 tb20 tb10 tb11 tb21 tb21 tb11 tb12 tb22 tb22 tb12 tb13 tb23 tb23 tb13 tb14 tb24 tb24 tb14 tb15 tb25 tb25 tb15 tb16 tb26 tb26 tb16 tc10 tc20 tc20 tc10 tc11 tc21 tc21 tc11 tc12 tc22 tc22 tc12 tc13 tc23 tc23 tc13 tc14 tc24 tc24 tc14 tc15 tc25 tc25 tc15 tc16 tc26 tc26 tc16 td10 td20 td20 td10 td11 td21 td21 td11 td12 td22 td22 td12 td13 td23 td23 td13 td14 td24 td24 td14 td15 td25 td25 td15 td16 td26 td26 td16 te10 te20 te20 te10 te11 te21 te21 te11 te12 te22 te22 te12 te13 te23 te23 te13 te14 te24 te24 te14 te15 te25 te25 te15 te16 te26 te26 te16
THC63LVD1023B_rev.3.0_e copyright?2011 thine electronics, inc. 24/26 thine electronics, inc. note 1)cable connection and disconnection don't connect and disconnec t the lvds cable, when the powe r is supplied to the system. 2)gnd connection connect the each gnd of the pcb which THC63LVD1023B and lvds-rx on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3)multi drop connection multi drop connection is not recommended. 4)asynchronous use asynchronous use such as following systems are not recommended. lvds-rx THC63LVD1023B lvds-rx tclk+ tclk- THC63LVD1023B THC63LVD1023B ic clkout clkout data data lvds-rx lvds-rx ic tclk+ tclk- tclk+ tclk- clkout data data THC63LVD1023B THC63LVD1023B ic tclk+ tclk- tclk+ tclk- clkout clkout data data ic
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 25/26 thine electronics, inc. package 0.25mm gage plane 22.00 bsc. 20.00 bsc. 22.00 bsc. 20.00 bsc. 17.50 0.50 bsc. 0.20 +0.07/-0.03 17.50 0.10 s s seating plane 1.60 max 1.40 +/-0.05 0.05~0.15 1.00 ref 0.09~0.20 0.60 +/-0.15 0.20 min 3.5+/-3.5 degree index unit:mm THC63LVD1023B
THC63LVD1023B _rev.3.0_e copyright?2011 thine electronics, inc. 26/26 thine electronics, inc. notices and requests 1.)the product specifications described in this mate rial are subject to cha nge without prior notice. 2.)the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions s hould be found in this mate rial, we may not be able to correct them immediately. 3.)this material contains our c opy right, know-how or other pr oprietary. copying or disclosing to third parties the contents of this material without our prior perm ission is prohibited. 4.)note that if infringe ment of any third party' s industrial ownership s hould occur by using this product, we will be exempted from the responsibil ity unless it directly re lates to the production pro- cess or functions of the product. 5.)this product is presumed to be used for general electric eq uipment, not for the applications which require very high reliability (including medi cal equipment directly concerning people's life, aerospace equipmen t, or nuclear control equi pment). also, when using this product for the equip- ment concerned with the control and safety of the transportation means, the traffic signal equip- ment, or various types of safety equipment, please do it after appl ying appropriate m easures to the product. 6.)despite our utmost efforts to im prove the quality and re liability of the product, faults will occur with a certain small probability, which is inevitable to a semi-c onductor product. therefore, you are encouraged to have suffic iently redundant or error preventive de sign applied to the use of the prod- uct so as not to have our product cause any social or public damage. 7.)please note that this product is not designed to be radiation-proof. 8.)customers are asked, if required, to judge by themselves if th is product falls under the category of strategic goods under the foreign exch ange and foreign trade control law. thine electronics, inc. e-mail: sales@thine.co.jp

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